1. Field of Invention
The present invention relates to pulse width modulated power supplies and, more particularly, to paralleled buck converters employing an interwoven inductor scheme to improve power conversion efficiency.
2. Related Art
With reference to FIG. 1, prior art buck converters employing synchronous rectification include a series pass element, for example, a MOSFET QA and a shunt element, for example, a MOSFET QB operating in synchronism to produce a pulse width modulated signal for input to an inductor L coupled in series with a capacitor C. As is known in the art, a control circuit 10 produces gate drive signals for input to the MOSFETs QA, QB, such that the MOSFETs are alternately biased on and off to couple either Vin or ground to the inductor L, thereby producing the pulse width modulated signal.
The control 10 receives a feedback signal VFB from a resistor divider network comprising R1 and R2, such that a sample of the output voltage VO is fed back to the control 10 so that the control 10 may make appropriate modifications to the timing of the gate drive signals to the MOSFETs QA, QB.
The inductor L and capacitor C produce a second order output filter which filters the high frequency components from the pulse width modulated signal input to the inductor L such that a relatively smooth DC voltage is produced at VO. Further, since the resistor divider R1, R2 and control 10 provide a feedback voltage control, the DC voltage at VO is also regulated. As is known in the art, Vo=D.times.Vin, where D is the duty cycle of the pulse width modulated signal. Thus, Vout is less than or equal to Vin.
It is known that the current flowing through inductor L is substantially triangular with inflection points being substantially coincident with the switching times of the MOSFETs QA, QB. In order to meet ripple voltage requirements of the converter, a substantially large capacitor C must be selected to filter out voltage ripple which would result from the current ripple through the inductor L.
Unfortunately, in order to substantially reduce the voltage ripple at VO, excessively large capacitors C and/or inductors L must be employed which result in excessive cost and low power density of the convertor. Although the voltage ripple VO may be reduced by increasing the switching frequency of the MOSFETs QA, QB, such increases in switching frequency also result in increases in switching losses which also reduces the efficiency of the converter. The circuit shown in FIG. 1 typically has a n efficiency of about 85%.
Accordingly, there is a need in the art for a buck power converter which substantially reduces the ripple voltage at the output, VO, while also improving efficiency of the converter.